1. Field of the Invention
The invention relates to a circuit for reducing the latch-up sensitivity in complementary MOS technology, including a first MOS transistor of a first conduction type being disposed in a semiconductor substrate having a complementary second conduction type; a second MOS transistor of the second conduction type being disposed in a well of the first conduction type in the semiconductor substrate; the semiconductor substrate and the source structure of the first transistor being connected to a first supply potential; and the well and the source structure of the second; transistor being connected to a second supply potential.
2. Description of the Related Art
The danger of a latch-up effect is known and described in the literature (R. Troutman, Latch-up in CMOS Technology, Kluwer Academic Publishers 1986; and R. Muller, Device Electronics for Integrated Circuits, Wiley 1986) regarding CMOS technology. The term latch-up effect refers to the firing of a parasitic thyristor, which is formed by adjacent complementary transistors of the CMOS circuit and the resultant pnpn structure. The parasitic thyristor is composed of two bipolar transistors and is blocked under normal operating conditions. Such a device is more fully discussed below in the description of the drawings.
It is known to place an additional doped zone, known as a guard ring, between the two complementary transistors and to connect it to a predetermined potential, in order to siphon off the charge carriers and suppress a latch-up effect caused by minority carriers. This is particularly advantageous if a weakly doped semiconductor layer is applied, for instance by epitaxia, onto a highly doped semiconductor substrate, and the MOS transistors are disposed in such a high-impedance semiconductor layer. Minority carriers will then remain in that weakly doped layer, because they are exposed to less resistance at that location than in the highly doped substrate. A circuit of that kind is known from the aforementioned publication by R. Troutman on page 167 and is discussed in more detail below in the description of the drawings.
It is accordingly an object of the invention to provide a circuit for reducing the latch-up sensitivity of a CMOS circuit, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which minority carriers injected into the substrate are removed with high effectiveness and the latch-up sensitivity is reduced, even in the event of major disturbances at the output level.